1. Field of the Invention
The invention relates to the field of integrated semiconductor circuits. More particularly, the invention relates to the field of high speed input logic receivers such as Complementary Metal Oxide Semiconductor (CMOS) input receivers or pseudo-differential input receivers.
2. Description of Related Art
Generally, a conventional CMOS input receiver, such as those that do not support an additional reference voltage, Vref, as shown in FIG. 1 using thick devices or using thin devices, works well below 200 MHz for low power memory interface such as those defined in External Bus Interface standards EBI1, EBI2, and the like. For higher frequency operation, such as from 200 MHz to 533 MHz, several kinds of Vref-based single-ended pseudo-differential input receiver as shown in FIG. 2 have been used with different Vref values, such as one-half the supply voltage without parallel termination or 70% supply voltage with a Vddq-termination. To cover wide-range frequency and support for Vref, such as required for receiver implementations in support of a low power Double Data Rate (DDR2) interface, a simple solution is to configure multiple parallel input receivers and to turn on only one receiver based on the Vref value. This approach, however, is not desirable in terms of area and power. Additionally, the multiple parallel receiver implementation suffers from performance degradation that can be attributable to the increased input capacitance, Cin, and the increased input-path delay due to the added mux.